1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device whose memory area is constituted by a plurality of banks.
2. Description of the Prior Art
Generally, in a conventional semiconductor memory device such as a DRAM, memory cells are formed at the intersections of a plurality of bit line pairs and a plurality of word lines. Memory information of a target memory cell can be read out by selecting a word line by a row address and a bit line pair by a column address.
In a conventional semiconductor memory device such as a DRAM, the memory area is divided into a plurality of blocks due to an increase in memory capacity and limitations on the length of the bit line pair.
To read out memory information stored in the memory cell of the semiconductor memory device constituted by a plurality of blocks, a row address is first designated, and then a column address and block address are designated. After the addresses are designated, various operations such as a data write and read are performed upon reception of external commands.
FIG. 1 is a block diagram showing a semiconductor memory device constituted by a plurality of blocks as the first prior art.
In this conventional semiconductor memory device, the memory area is made up of two blocks 121 and 122.
The semiconductor memory device comprises the blocks 121 and 122, an address buffer 91, and a timing control circuit 93.
When a row address activation signal 30 becomes active, the timing control circuit 93 activates an address enable signal 100 and changes a word line drive signal 97, a precharge signal 98, and a sense amplifier enable signal 99 from high level (to be referred to as H hereinafter) to low level (to be referred to as L hereinafter) or from L to H at predetermined timings in a predetermined order.
The row address activation signal 30 is activated by an external command.
When the address enable signal 100 becomes active, the address buffer 91 latches and outputs a row address included in an address signal 32 as a row address signal 33, and changes a block selection signal 90.sub.1 or 90.sub.2 to H in order to activate a block designated by the block address of the address signal 32.
The block 121 is constituted by bit line pairs 41.sub.1 to 41.sub.n, word lines 40.sub.1 to 40.sub.m, an SAP, an SAN, a plurality of memory cells 17 respectively arranged at the intersections of the bit line pairs 41.sub.1 to 41.sub.n and word lines 40.sub.1 to 40.sub.m, precharge circuits 18.sub.1 to 18.sub.n respectively arranged on the bit line pairs 41.sub.1 to 41.sub.n, a precharge circuit 19 arranged between the SAP and SAN, sense amplifiers 29.sub.1 to 29.sub.n respectively arranged on the bit line pairs 41.sub.1 to 41.sub.n, a row decoder 115.sub.1, an AND circuit 101, an OR circuit 102, an inverter 103, an AND circuit 104, an inverter 42, a p-channel MOS transistor 38, and an n-channel MOS transistor 39.
The AND circuit 101 ANDs the word line drive signal 97 and a block selection signal 90.sub.1 and outputs the AND as a word line drive signal 7.sub.1.
When the word line drive signal 7.sub.1 changes to H, the row decoder 115.sub.1 activates a word line designated by the row address signal 33 from the word lines 40.sub.1 to 40.sub.m.
As shown in FIG. 2, the row decoder 115.sub.1 is made up of address decoders 140.sub.1 to 140.sub.m.
The address decoders 140.sub.1 to 140.sub.m are respectively arranged for the word lines 40.sub.1 to 40.sub.m. In the address decoders 140.sub.1 to 140.sub.m, the addresses of corresponding word lines are set. When the word line drive signal 7.sub.1 changes to H, the address decoders 140.sub.1 to 140.sub.m operate. If an address indicated by the row address signal 33 is a set address, each address decoder activates a corresponding word line.
The inverter 103 inverts the logic of the block selection signal 90.sub.1 and outputs the inverted signal.
The OR circuit 102 ORs the output signal from the inverter 103 and the precharge signal 98 and outputs the OR.
When the output signal from the OR circuit 102 changes to H, the precharge circuits 18.sub.1 to 18.sub.n precharge the bit line pairs 41.sub.1 to 41.sub.n, fix them to a constant potential level, and keep them at the same level.
Similarly, when the output signal from the OR circuit 102 changes to H, the precharge circuit 19 precharges the SAP and SAN, fixes them at a constant potential level, and keeps them at the same level.
The AND circuit 104 ANDs the sense amplifier enable signal 99 and the block selection signal 90.sub.1 and outputs the AND as a sense amplifier enable signal 9.sub.1.
The inverter 42 inverts the logic of the sense amplifier enable signal 9.sub.1.
The output signal from the inverter 42 is input to the gate of the p-channel MOS transistor 38. When the output signal from the inverter 42 changes to L, the p-channel MOS transistor 38 is turned on to apply a voltage VDD to the SAP.
The sense amplifier enable signal 9.sub.1 is input to the gate of the n-channel MOS transistor 39. When the sense amplifier enable signal 9.sub.1 changes to H, the n-channel MOS transistor 39 is turned on to apply a ground voltage to the SAN.
When both the p-channel MOS transistor 38 and n-channel MOS transistor 39 are turned on, the sense amplifiers 29.sub.1 to 29.sub.n operate to amplify the voltage output to the bit line pairs 41.sub.1 to 41.sub.n and externally output the amplified voltage via a column selection circuit and input/output circuit (neither is shown).
The block 122 has the same arrangement as that of the block 121 except that a block selection signal 90.sub.2 is input instead of the block selection signal 90.sub.1, and a description thereof will be omitted.
Operation of the conventional semiconductor memory device will be explained with reference to FIGS. 1 and 2 and a timing chart of FIG. 3.
The following description concerns a read, and a write is similarly performed.
Operation for reading out data of the memory cell 17 formed at the intersection of the bit line pair 41.sub.1 and word line 40.sub.1 in the block 121 will be explained.
When an external command and the address signal 32 are input at t.sub.41, the external command activates the row address activation signal 30, and the timing control circuit 93 activates the address enable signal 100. The address buffer 91 latches and outputs the row address of the address signal 32 as the row address signal 33. A blank portion of the address signal 32 in FIG. 3 represents the location of the row address read as the row address signal 33. Since the block address indicates the block 121, the address buffer 91 changes the block selection signal 90.sub.1 to H.
At t.sub.42, the timing control circuit 93 changes the precharge signal 98 to L to change the precharge signal 8.sub.1 to L, thereby inactivating the precharge circuits 18.sub.1 to 18.sub.n and the precharge circuit 19. The timing control circuit 93 changes the word line drive signal 97 to H to change the word line drive signal 7.sub.1 to H, thereby activating the word line 40.sub.1. At t.sub.43, the timing control circuit 93 changes the sense amplifier enable signal 99 to H to change the sense amplifier enable signal 9.sub.1 to H. thereby turning on the p-channel MOS transistor 38 and the n-channel MOS transistor 39 and activating the sense amplifiers 29.sub.1 to 29.sub.n.
As a result, data stored in the memory cell 17 formed at the intersection of the bit line pair 41.sub.1 and word line 40.sub.1 is output to the sense amplifier 29.sub.1 via the bit line pair 41.sub.1 and amplified, and the amplified data is output.
After the data is read out, the block 121 is inactivated. More specifically, at t.sub.44, the timing control circuit 93 changes the word line drive signal 97 to L to change the word line drive signal 7.sub.1 to L, thereby inactivating the word line 40.sub.1. At t.sub.45, the timing control circuit 93 changes the sense amplifier enable signal 99 to L to change the sense amplifier enable signal 9.sub.1 to L, thereby inactivating the sense amplifiers 29.sub.1 to 29.sub.n. At t.sub.46, the timing control circuit 93 changes the precharge signal 98 to H to change the precharge signal 8.sub.1 to H, thereby activating the precharge circuits 18.sub.1 to 18.sub.n and 19. That is, the bit line pair 41.sub.1, SAP, and SAN are charged to a given voltage, and voltages across lines are set to the same level.
However, if the semiconductor memory device is constituted by a plurality of blocks, and signals are controlled by one timing control circuit 93, while a certain block is processed, another block cannot be processed. As the memory capacity and the number of blocks increase, a longer time is undesirably spent to read out memory contents.
To solve this problem, a semiconductor memory device is constituted by not a plurality of blocks but banks capable of operating independently of each other.
A semiconductor memory device constituted by a plurality of banks according to the second prior art will be described with reference to FIG. 4. The same reference numerals as in FIG. 1 denote the same parts.
In this semiconductor memory device, the memory area is made up of four divided banks 171 to 174.
The conventional semiconductor memory device is constituted by the banks 171 to 174, timing control circuits 110.sub.1 to 110.sub.4 respectively arranged for the banks 171 to 174, latch circuits 111.sub.1 to 111.sub.4 respectively arranged for the timing control circuits 110.sub.1 to 110.sub.4, a row address buffer 45, and a bank decoder 143.
The row address buffer 45 outputs the row address of an address signal 32 as a row address signal 33.
The bank decoder 143 activates for a predetermined time bank selection signals 11.sub.1 to 11.sub.4 for activating a bank indicated by the bank address of the address signal 32.
The latch circuits 111.sub.1 to 111.sub.4 read a row address activation signal 30 and a row address inactivation signal 31 only when the corresponding bank selection signals 11.sub.1 and 11.sub.4 are active. If the row address activation signal 30 becomes active, the latch circuits 111.sub.1 to 111.sub.4 activate a row address activation signal 112.sub.1. If the row address inactivation signal 31 becomes active, the latch circuits 111.sub.1 to 111.sub.4 inactivate the row address activation signal 112.sub.1.
The timing control circuits 110.sub.1 to 110.sub.4 perform the same operation as that of the timing control circuit 93 in FIG. 1 except that they do not output the address enable signal 100. The timing control circuits 110.sub.1 to 110.sub.4 output word line drive signals 7.sub.1 to 7.sub.4 instead of the word line drive signal 97, output precharge signals 8.sub.1 to 8.sub.4 instead of the precharge signal 98, output sense amplifier enable signals 9.sub.1 to 9.sub.4 instead of the sense amplifier enable signal 99, and receive the row address activation signal 112.sub.1 instead of the row address activation signal 30.
The bank 171 is constituted by bit line pairs 41.sub.1 to 41.sub.n, word lines 40.sub.1 to 40.sub.m, an SAP, an SAN, a plurality of memory cells 17 respectively formed at the intersections of the bit line pairs 41.sub.1 to 41.sub.n and word lines 40.sub.1 to 40.sub.m, precharge circuits 18.sub.1 to 18.sub.n respectively arranged on the bit line pairs 41.sub.1 to 41.sub.1, a precharge circuit 19 arranged between the SAP and SAN, sense amplifiers 29.sub.1 to 29.sub.n respectively arranged on the bit line pairs 41.sub.1 to 41.sub.n, a row decoder 135.sub.1, an inverter 42, a p-channel MOS transistor 38, and an n-channel MOS transistor 39.
When the word line drive signal 7.sub.1 changes to H, the row decoder 135.sub.1 latches the row address signal 33 in accordance with the bank selection signal 11.sub.1, and activates a word line designated by the row address signal 33 from the word lines 40.sub.1 to 40.sub.m.
As shown in FIG. 5, the row decoder 135.sub.1 is made up of address decoders 140.sub.1 to 140.sub.m and a latch circuit 141.sub.1.
The latch circuit 141.sub.1 latches and outputs the row address signal 33 in accordance with the bank selection signal 11.sub.1. The address decoders 140.sub.1 to 140.sub.m receive the row address signal 33 latched and output by the latch circuit 141.sub.1.
Operation of the semiconductor memory device according to the second prior art will be described.
Operation for reading out data of the memory cell 17 formed at the intersection of the bit line pair 41.sub.1 and word line 40.sub.1 in the bank 171 will be explained.
The row address activation signal 30 becomes active, and the address signal 32 including a row address indicating the address of the word line 40.sub.1 and a bank address indicating the bank 171 is externally input. Then, the row address buffer 45 outputs the row address of the address signal 32 as the address signal 33, and the bank decoder 143 activates the bank selection signal 11.sub.1.
Since the bank selection signal 11.sub.1 and row address activation signal 30 become active, the latch circuit 111.sub.1 activates the row address activation signal 112.sub.1.
Since the row address activation signal 112.sub.1 becomes active, the timing control circuit 110.sub.1 controls the word line drive signal 7.sub.1, precharge signal 8.sub.1, and sense amplifier enable signal 9.sub.1 to perform a read from the memory cell 17 and inactivation after the read.
At this time, since the bank selection signal 11.sub.1 is active, the row decoder 135.sub.1 latches the row address signal 33 and activates the word line 40.sub.1 indicated by the latched row address signal 33.
Operation for designating inactivation of the bank 172 while reading out data stored in the memory cell 17 in the bank 171 will be explained.
The bank address included in the address signal 32 input externally is switched to designate the bank 172. The bank decoder 143 inactivates the bank selection signal 11.sub.1 and activates the bank selection signal 11.sub.2. The latch circuit 111.sub.1 keeps the row address activation signal 112.sub.1 active regardless of changes in row address activation signal 30 and row address inactivation signal 31 by the inactive bank selection signal 11.sub.1. The row decoder 135.sub.1 also keeps the word line 40.sub.1 active regardless of changes in row address signal 33 by the inactive bank selection signal 11.sub.1. In this manner, in the bank 171, data can be read out regardless of changes in row address signal.
Since the bank selection signal 11.sub.2 and row address inactivation signal 31 become active, the bank 172 is inactivated.
Operation for simultaneously performing a data read of the bank 171 and inactivation of the bank 172 has been described above. Similarly, in the conventional semiconductor memory device, a data read or inactivation of a given bank and a data read or inactivation of another bank can be simultaneously performed.
However, the semiconductor memory device according to the second prior art requires timing control circuits equal in number to the banks. As the number of banks increases, the number of timing control circuits also increases accordingly.
FIG. 6 shows an example of a general timing control circuit.
A timing control circuit 192 shown in FIG. 6 is constituted by delay circuits 191.sub.1 to 191.sub.3 and drivers 190.sub.1 to 190.sub.3. The timing control circuit 192 receives an input signal 194 and outputs control signals 193.sub.1 to 193.sub.3 at different timings.
Each of the delay circuits 191.sub.1 to 191.sub.3 is made up of a plurality of series-connected inverters. The delay circuits 191.sub.1 to 191.sub.3 are also series-connected to each other. An output from the delay circuit 191.sub.1 is output as the control signal 193.sub.1 via the driver 190.sub.1. An output from the delay circuit 191.sub.2 is output as the control signal 193.sub.2 via the driver 190.sub.2. An output from the delay circuit 191.sub.3 is output as the control signal 193.sub.3 via the driver 190.sub.3.
The control signals 193.sub.1 to 193.sub.3 correspond to the word line drive signal 7.sub.1, precharge signal 8.sub.1, and sense amplifier enable signal 9.sub.1.
Since the drivers 190.sub.1 to 190.sub.3 supply signals delayed by the delay circuits 191.sub.1 to 191.sub.3 as the control signals 193.sub.1 to 193.sub.3 to respective circuits, the timing control circuit 192 must use large inverters. Consequently, the occupied area of the timing control circuit is generally larger than the occupied area of another circuit. As the number of banks increases to 4, 8, 16, . . . along with an increase in memory capacity of recent semiconductor memory devices, the circuit area of the timing control circuit greatly increases.
The semiconductor memory device according to the second prior art requires the timing control circuits equal in number to the banks. For this reason, as the number of banks increases, the circuit area of the timing control circuits greatly increases.